The present invention relates to the structural organization of MOSFET pairs and, more particularly, to MOSFET pairs having reduced PCB mounting area requirements, increased thermal efficiency, and reduced parasitic impedances.
Multi-die packaging is common in power converters in which MOSFET switching transistors are used; for example and as shown in FIGS. 1 and 1A, a circuit assembly or package 10 includes a first FET 12 and a second FET 14 in a side-by-side or lateral mounting arrangement on a common plane with a controller or driver chip 16 that is connected via bonding wires 18 between conductive pads (unnumbered) on the driver chip 16 and to contacts 20 of the respective leadframe portions and by bonding wires 18 connected to various contact pads (unnumbered) on the FET structures. A first strap or clip 22, typically formed from shape-sustaining copper or a copper alloy in ribbon or ribbon-like form, is in electrical and thermal contact with the upper surface of the FET 14 and a second clip 24 is in electrical and thermal contact with the upper surface of the FET 12. As shown in FIG. 1A, the first clip 24 is generally “L-shaped” and includes a columnar portion (unnumbered) that is in contact with a contact pad 26 of the leadframe; the clip 24 is similarly shaped and is in contact with another portion (unnumbered) of the leadframe. In typical power converter operations, the clips 22 and 24 serve as substantial current carrying conductors as well as heat sinks. While not specifically shown, the various parts are electrically connecting using solder-bonding techniques. As shown in FIG. 1A at 28, the structure of FIG. 1 is typically encapsulated in a thermosetting molding compound to define a circuit package.
The MOSFET package shown in FIGS. 1 and 1A finds use in power switching applications including use in synchronous buck converter circuits of the type shown in FIGS. 1B and 1C. In FIG. 1B, two n-channel MOSFETs, FEThigh and FETlow, are in series circuit between Vin and ground GND with a switching or phase node PN defined between the source S of FEThigh and the drain D of FETlow. The drain D of FEThigh is connected to Vin while the source S of FETlow is connected to ground. The two FETs are alternatively turned on and off by respective on/off pulses of appropriate pulse width and timing from a driver circuit 16 to their gates G to step-down Vin into an inductor I. The circuit of FIG. 1C is similar to that of FIG. 1B except that the high-side FET is a p-channel MOSFET with its drain D connected to the drain D of FETlow to define the phase node PN; in FIG. 1C, the FEThigh and FETlow are alternatively turned on and off by respective pulses of appropriate pulse width and timing to their gates G from a driver circuit 16 to switch Vin into an inductor I. The inductor I can take the form of a planar spiral inductor formed on a substrate or a discrete inductor package. While not specifically shown, the side of the inductor I opposite to that connected to the phase node PN can be connected to one or more capacitors (and/or inductors) to smooth or otherwise condition the output.
The physical organization of FIG. 1 functions for its intended purpose; however, the side-by-side organization of FIG. 1 militates against more compact circuit packages occupying smaller circuit board areas.